We are a team focused on developing high-speed broadband communication systems, with a primary emphasis on SerDes physical interfaces (HDMI, USB, PCIe, MPHY). Our involvement spans all stages of product development, from defining the system-level architecture and algorithmic specification to optimizing performance and verifying mixed-signal functionality. We also conduct hands-on silicon validation.
Main Responsibilities:
* Architecture and algorithmic specification
* Mixed signal modeling and verification using System Verilog
* Silicon test, correlation studies and validation
Key Qualifications:
* A Master's or Ph.D. in Electronics or Electrical and Computer Engineering
* Familiarity with CMOS analog and digital circuits, including filters
* Familiarity with digital IC design and verification using simulation tools such as VCS
* A solid background in Electronics and Computer Architecture
* Experience in C/Matlab/System Verilog modeling of circuits and systems
* Knowledge of script languages such as Python
Nice to Have Experience:
* A background in Control and/or Communications theory is beneficial – control loops and dynamics, equalization, coding, noise/crosstalk filtering
* Experience in bare metal programming is advantageous - Assembly/interaction with configuration registers
* Knowledge of digital verification methodologies such as UVM
* Knowledge of digital and mixed signal simulation and verification tools such as XA, SpyGlass and Formality
* Knowledge of circuit topologies in high-speed Rx/Tx SerDes PHY
* Knowledge of high-speed analog CMOS circuit design and CDR architectures